Projects
FLOATING POINT ADDER MULTIPLIER USING FIFO, SJSU, September 2017
- By Prabhjot Bhathal
- Feb 14, 2018
Skills
verilog ASIC Design CMOSCompany
San Jose State University• Assignment to design FIFO and use it in given Floating Point Adder Multiplier using Verilog and Synthesize at 250 MHz.