Projects

Oracle Ecommerce eBook

Working with TopRank Marketing, created a 68-page ebook, resulting in a 15% conversion rate surpassing the client's 5% goal.

Feb 20, 2018

Budget Breakdown Calculator

Created a HTML form that allows users to input their monthly expenses and calculates the user’s excess budget or overspending. Utilized Chart.js to render a ...

Feb 20, 2018

Widgets

Feb 20, 2018

Todo List App

Feb 20, 2018

OkCupet

Implemented an algorithm to create compatibility percentages between the user and the adoptable pets. Created a messaging feature to allow users to send mess...

Feb 20, 2018

CVS Caremark - AETNA merger of pharmacy units

* Supported the integration of IT Systems between to major healthcare corporations as part of a Deloitte Commercial Consulting team * Updated, monitored an...

Feb 19, 2018

About Evan Hudgins

A big brother with Big Brothers Big Sisters, Evan Drake Hudgins studies at the University of Oklahoma, where he will graduate this spring with a business adm...

Feb 16, 2018

Mobil Court Refurbishment Residential Project

Mobil Court Refurbishment Residential Project is a 52 units (9 story -$ 110M)

Feb 14, 2018

Black Diamond Residential Project

Black Diamond Residential Project is a 250 unit (14 story-$132.6M)

Feb 14, 2018

Temperature Controller

I built a device that reads the temperature from a digital sensor via I2C and toggles a chest freezer on/off to regulate the temperature of a fermentation ve...

Feb 14, 2018

Student Loan Payoff Calculator

I made an application that will pull student loan data either from a file or from a website. It then calculates the payoff date and interest paid for a payer...

Feb 14, 2018

TRANSMISSION GATE LOGIC BASED 32:1 MUX CIRCUIT USING CADENCE

• Individual Project. Created a 32:1 MUX circuit using Cadence in Cadence Virtuoso. • Aimed to understand Cadence Virtuoso and apply CMOS circuit's knowledge...

Feb 14, 2018

64-Bit CONDITIONAL SUM and CARRY SELECT ADDERS

• Individual Project. Implemented, analyzed, simulated, synthesized and post-synthesized 64-bit Conditional Sum and Carry Select Adders in Verilog using EDA ...

Feb 14, 2018

FLOATING POINT ADDER MULTIPLIER USING FIFO, SJSU, September 2017

• Assignment to design FIFO and use it in given Floating Point Adder Multiplier using Verilog and Synthesize at 250 MHz.

Feb 14, 2018

LOOK BACK COMPRESSOR, SJSU, Oct-Nov 2017

• Group Project aiming to design a look back compressor to polish Verilog skills, use ASIC CMOS design's knowledge such as FIFO and Memory. Synthesize design...

Feb 14, 2018